This invention relates to a high voltage integrated semiconductor device having high voltage semiconductor elements which are isolated from each other by grooves. This structure increases the breakdown voltage across the high voltage semiconductor elements that form the semiconductor integrated circuit.
The dielectric isolating technique shown in FIG. 1 has been used for the purpose of increasing the breakdown strength to a value higher than several hundreds volts impressed across a plurality of high voltage semiconductor elements formed on a silicon monocrystalline substrate.
In the semiconductor device shown in FIG. 1, island regions 1 made of monocrystalline silicon and containing semiconductor element regions 4a and 4b are formed on such insulating films 2 as oxide films or nitride films which are formed on a polycrystalline silicon substrate 3. The insulating strength between the elements is afforded by the substrate 3.
Such a dielectric isolation method, however, requires extremely complicated steps of manufacturing the isolating substrate.
Where the semiconductor element regions 4a and 4b are formed in the island regions by a diffusion technique, there is such disadvantage that the substrate 3 undergoes deformation due to the difference in the thermal expansion coefficients of the island regions 1 and of the substrate 3 so that it is impossible to ensure high accuracy mask alignment during a photolithographic step in the wafer treatment.
Furthermore, crystal strains in the substrate caused by the deformation of the substrate decrease the junction breakdown strength in respective semiconductor elements and deteriorate other characteristics, which decreases the yield of satisfactory semiconductor devices.